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873032am www.icst.com/products/hiperclocks.html rev. a august 11, 2004 1 integrated circuit systems, inc. ICS873032 h igh s peed , 2 d ifferential - to - 3.3v, 5v lvpecl/ecl c lock g enerator preliminary g eneral d escription the ICS873032 is a high speed, high perfor- mance differential-to-3.3v, 5v lvp ecl/ecl clock generator and a member of the hiperclocks? family of high performance clock solutions from ics. the ICS873032 is characterized to operate from either a 3.3v for a 5v power supply. f eatures ? 1 differential 3.3v, 5v lvpecl / ecl output ? 1 differential pclk, npclk input pair ? pclk, npclk pair can accept the following differential input levels: lvpecl, lvds, cml, sstl ? input frequency: 4ghz ? translates any single ended input signal to 3.3v lvpecl levels with resistor bias on npclk input ? lvpecl mode operating voltage supply range: v cc = 3.0v to 5.5v, v ee = 0v ? ecl mode operating voltage supply range: v cc = 0v, v ee = -5.5v to -3.0v ? -40c to 85c ambient operating temperature ? pin compatible with mc100ep32 b lock d iagram p in a ssignment ICS873032 8-lead soic 3.90mm x 4.90mm x 1.37mm package body m package top view reset pclk npclk v bb 1 2 3 4 hiperclocks? ics vcc q nq v ee 8 7 6 5 q nq reset pclk npclk v bb ICS873032 8-lead tssop, 118 mil 3mm x 3mm x 0.95mm package body g package top view 2 the preliminary information presented herein represents a product in prototyping or pre-production. the noted characteristics a re based on initial product characterization. integrated circuit systems, incorporated (ics) reserves the right to change any circuitry or specific ations without notice.
873032am www.icst.com/products/hiperclocks.html rev. a august 11, 2004 2 integrated circuit systems, inc. ICS873032 h igh s peed , 2 d ifferential - to - 3.3v, 5v lvpecl/ecl c lock g enerator preliminary t able 1. p in d escriptions t able 2. p in c haracteristics r e b m u ne m a ne p y tn o i t p i r c s e d 1t e s e rt u p n in w o d l l u p. s l e v e l e c a f r e t n i l c e p v l h 0 0 1 d e d n e - e l g n i s . n i p t e s e r 2k l c pt u p n in w o d l l u p . s l e v e l e c a f r e t n i l c e p v l . g n i t a o l f t f e l n e h w w o l t l u a f e d . t u p n i k c o l c 3k l c p nt u p n in w o d l l u p. s l e v e l e c a f r e t n i l c e p v l . t u p n i k c o l c 4v b b t u p t u o. e g a t l o v s a i b 5v e e r e w o p. n i p y l p p u s e v i t a g e n 7 , 6q , q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 8v c c r e w o p. n i p y l p p u s e v i t i s o p : e t o n n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t s r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 5 7k ? t able 3. t ruth t able s t u p n is t u p t u o k l c pk l c p nt e s e rqq n xx z lh zz nlff n o i t s i s n a r t h g i h o t w o l = z n o i t s i s n a r t w o l o t h g i h = z n n o i t c n u f 2 y b e d i v i d = f t rr f igure 1. t iming d iagram pclk reset q
873032am www.icst.com/products/hiperclocks.html rev. a august 11, 2004 3 integrated circuit systems, inc. ICS873032 h igh s peed , 2 d ifferential - to - 3.3v, 5v lvpecl/ecl c lock g enerator preliminary t able 4a. p ower s upply dc c haracteristics , v cc = 3.0v to 5.5v; v ee = 0v l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e v i t i s o p 0 . 33 . 35 . 5v i e e t n e r r u c y l p p u s r e w o p 2 2a m a bsolute m aximum r atings t able 4b. lvpecl dc c haracteristics , v cc = 3.3v; v ee = 0v note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifi- cations only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maxi- mum rating conditions for extended periods may affect product reliability. supply voltage, v cc 6v (lvpecl mode, v ee = 0) negative supply voltage, v ee -6v (ecl mode, v cc = 0) inputs, v i (lvpecl mode) -0.5v to v cc + 0.5v inputs, v i (ecl mode) 0.5v to v ee - 0.5v outputs, i o continuous current 50ma surge current 100ma v bb sink/source, i bb 0.5ma operating temperature range , ta -40c to +85c storage temperature, t stg -65c to 150c package thermal impedance, ja 112.7c/w (0 lfpm) (junction-to-ambient) for 8 lead soic package thermal impedance, ja 101.7c/w (0 m/s) (junction-to-ambient) for 8 lead tssop l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 5 7 1 . 25 7 2 . 28 3 . 25 2 2 . 25 9 2 . 27 3 . 25 9 2 . 23 3 . 25 6 3 . 2v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 0 4 . 15 4 5 . 18 6 . 15 2 4 . 12 5 . 15 1 6 . 14 4 . 15 3 5 . 13 6 . 1v v h i e g a t l o v h g i h t u p n i ) d e d n e - e l g n i s ( 5 7 0 . 26 3 . 25 7 0 . 26 3 . 25 7 0 . 26 3 . 2v v l i e g a t l o v w o l t u p n i ) d e d n e - e l g n i s ( 3 4 . 15 6 7 . 13 4 . 15 6 7 . 13 4 . 15 6 7 . 1v v b b e c n e r e f e r e g a t l o v t u p t u o 6 8 . 18 9 . 16 8 . 18 9 . 16 8 . 18 9 . 1v v p p e g a t l o v t u p n i k a e p - o t - k a e p 0 5 10 0 80 0 2 10 5 10 0 80 0 2 10 5 10 0 80 0 2 1 m v v r m c e g a t l o v h g i h t u p n i 3 , 2 e t o n ; e g n a r e d o m n o m m o c 2 . 13 . 32 . 13 . 32 . 13 . 3v i h i t u p n i t n e r r u c h g i h k l c p n , k l c p 0 5 10 5 10 5 1a i l i t u p n i t n e r r u c w o l k l c p n , k l c p 0 1 -0 1 - 0 1 - a v h t i w 1 : 1 y r a v s r e t e m a r a p t u p t u o d n a t u p n i c c v . e e . v 5 . 0 - o t v 5 2 9 . 0 + y r a v n a c 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t c c . v 2 - v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . v s i k l c p n , k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e - e l g n i s r o f : 3 e t o n c c . v 3 . 0 +
873032am www.icst.com/products/hiperclocks.html rev. a august 11, 2004 4 integrated circuit systems, inc. ICS873032 h igh s peed , 2 d ifferential - to - 3.3v, 5v lvpecl/ecl c lock g enerator preliminary t able 4d. ecl dc c haracteristics , v cc = 0v; v ee = -5.5v to -3.0v t able 4c. lvpecl dc c haracteristics , v cc = 5v; v ee = 0v l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 5 2 1 . 1 -5 2 0 . 1 -2 9 . 0 -5 7 0 . 1 -5 0 0 . 1 -3 9 . 0 -5 0 0 . 1 -7 9 . 0 -5 3 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 9 8 . 1 -5 5 7 . 1 -2 6 . 1 -5 7 8 . 1 -8 7 . 1 -5 8 6 . 1 -6 8 . 1 -5 6 7 . 1 -7 6 . 1 -v v h i e g a t l o v h g i h t u p n i ) d e d n e - e l g n i s ( 5 2 2 . 1 -4 9 . 0 -5 2 2 . 1 -4 9 . 0 -5 2 2 . 1 -4 9 . 0 -v v l i e g a t l o v w o l t u p n i ) d e d n e - e l g n i s ( 7 8 . 1 -5 3 5 . 1 -7 8 . 1 -5 3 5 . 1 -7 8 . 1 -5 3 5 . 1 -v v b b e c n e r e f e r e g a t l o v t u p t u o 4 4 . 1 -2 3 . 1 -4 4 . 1 -2 3 . 1 -4 4 . 1 -2 3 . 1 -v v p p e g a t l o v t u p n i k a e p - o t - k a e p 0 5 10 0 80 0 2 10 5 10 0 80 0 2 10 5 10 0 80 0 2 1 m v v r m c e g a t l o v h g i h t u p n i 3 , 2 e t o n ; e g n a r e d o m n o m m o c v e e v 2 . 1 +0v e e v 2 . 1 +0v e e v 2 . 1 +0v i h i t u p n i t n e r r u c h g i h k l c p n , k l c p 0 5 10 5 10 5 1a i l i t u p n i t n e r r u c w o l k l c p n , k l c p 0 1 -0 1 -0 1 -a v h t i w 1 : 1 y r a v s r e t e m a r a p t u p t u o d n a t u p n i c c v . e e . v 5 . 0 - o t v 5 2 9 . 0 + y r a v n a c 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t c c . v 2 - v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . v s i k l c p n , k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e - e l g n i s r o f : 3 e t o n c c . v 3 . 0 + l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 5 7 8 . 35 7 9 . 38 0 . 45 2 9 . 35 9 9 . 37 0 . 45 9 9 . 33 0 . 45 6 0 . 4v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 0 1 . 35 4 2 . 38 3 . 35 2 1 . 32 2 . 35 1 3 . 34 1 . 35 3 2 . 33 3 . 3v v h i e g a t l o v h g i h t u p n i ) d e d n e - e l g n i s ( 5 7 7 . 36 0 . 45 7 7 . 36 0 . 45 7 7 . 36 0 . 4v v l i e g a t l o v w o l t u p n i ) d e d n e - e l g n i s ( 3 1 . 35 6 4 . 33 1 . 35 6 4 . 33 1 . 35 6 4 . 3v v b b e c n e r e f e r e g a t l o v t u p t u o 6 5 . 38 6 . 36 5 . 38 6 . 36 5 . 38 6 . 3v v p p e g a t l o v t u p n i k a e p - o t - k a e p 0 5 10 0 80 0 2 10 5 10 0 80 0 2 10 5 10 0 80 0 2 1 m v v r m c e g a t l o v h g i h t u p n i 3 , 2 e t o n ; e g n a r e d o m n o m m o c 2 . 152 . 152 . 15v i h i t u p n i t n e r r u c h g i h k l c p n , k l c p 0 5 10 5 10 5 1a i l i t u p n i t n e r r u c w o l k l c p n , k l c p 0 1 -0 1 - 0 1 - a v h t i w 1 : 1 y r a v s r e t e m a r a p t u p t u o d n a t u p n i c c v . e e . v 5 . 0 - o t v 5 2 9 . 0 + y r a v n a c 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t c c . v 2 - v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . v s i k l c p n , k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e - e l g n i s r o f : 3 e t o n c c . v 3 . 0 +
873032am www.icst.com/products/hiperclocks.html rev. a august 11, 2004 5 integrated circuit systems, inc. ICS873032 h igh s peed , 2 d ifferential - to - 3.3v, 5v lvpecl/ecl c lock g enerator preliminary t able 5. ac c haracteristics , v cc = 0v; v ee = -5.5v to -3.0v or v cc = 3.0 to 5.5v; v ee = 0v l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m f x a m y c n e u q e r f t u p n id b t4d b tz h g t d p 1 e t o n ; y a l e d n o i t a g a p o r pd b t0 0 4d b ts p t r r y r e v o c e r t e s e r / t e sd b t5 7 1d b ts p t r /t f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 2d b t0 6 1d b ts p t w p h t d i w e s l u pt e s e rd b t0 0 5d b ts p f t a d e r u s a e m e r a s r e t e m a r a p l l a . d e t o n e s i w r e h t o s s e l n u , z h g 7 . 1 . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n
873032am www.icst.com/products/hiperclocks.html rev. a august 11, 2004 6 integrated circuit systems, inc. ICS873032 h igh s peed , 2 d ifferential - to - 3.3v, 5v lvpecl/ecl c lock g enerator preliminary p arameter m easurement i nformation o utput l oad ac t est c ircuit d ifferential i nput l evel o utput d uty c ycle /p ulse w idth /p eriod p ropagation d elay o utput r ise /f all t ime v cmr cross points v pp v ee npclk v cc pclk scope qx nqx lvpecl 2v -3.5v to -1.0v clock outputs 20% 80% 80% 20% t r t f v swing t pd npclk q nq pclk v cc v ee pulse width t period t pw t period odc = q nq
873032am www.icst.com/products/hiperclocks.html rev. a august 11, 2004 7 integrated circuit systems, inc. ICS873032 h igh s peed , 2 d ifferential - to - 3.3v, 5v lvpecl/ecl c lock g enerator preliminary v cc - 2v 50 ? 50 ? rtt z o = 50 ? z o = 50 ? fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 a pplication i nformation f igure 2. s ingle e nded s ignal d riving d ifferential i nput 3.3v 125 ? 125 ? 84 ? 84 ? z o = 50 ? z o = 50 ? fout fin the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that gen- erate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock lay- outs may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for 3.3v lvpecl o utputs f igure 3b. lvpecl o utput t ermination f igure 3a. lvpecl o utput t ermination w iring the d ifferential i nput to a ccept s ingle e nded l evels vcc r2 1k v_ref c1 0.1u r1 1k single ended clock input pclk npclk figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609.
873032am www.icst.com/products/hiperclocks.html rev. a august 11, 2004 8 integrated circuit systems, inc. ICS873032 h igh s peed , 2 d ifferential - to - 3.3v, 5v lvpecl/ecl c lock g enerator preliminary lvpecl c lock i nput i nterface the pclk /npclk accepts lv pecl, cml, sstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 5a to 5f show interface examples for the hiperclocks pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver ter- mination requirements. f igure 4a. h i p er c lock s pclk/npclk i nput d riven by an o pen c ollector cml d river f igure 4b. h i p er c lock s pclk/npclk i nput d riven by a b uilt -i n p ullup cml d river f igure 4c. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river f igure 4f. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvds d river pclk/npclk 2.5v zo = 60 ohm sstl hiperclocks pclk npclk r2 120 3.3v r3 120 zo = 60 ohm r1 120 r4 120 2.5v f igure 4e. h i p er c lock s pclk/npclk i nput d riven by an sstl d river hiperclocks pclk npclk pclk/npclk 3.3v r2 50 r1 50 3.3v zo = 50 ohm cml 3.3v zo = 50 ohm 3.3v hiperclocks pclk npclk r2 84 r3 125 input zo = 50 ohm r4 125 r1 84 lvpecl 3.3v 3.3v zo = 50 ohm c2 r2 1k r5 100 zo = 50 ohm 3.3v 3.3v c1 r3 1k lvds r4 1k hiperclocks pclk npclk r1 1k zo = 50 ohm 3.3v pclk/npclk 3.3v r5 100 - 200 3.3v 3.3v hiperclocks pclk npclk r1 125 pclk/npclk r2 125 r3 84 c1 c2 zo = 50 ohm r4 84 zo = 50 ohm r6 100 - 200 3.3v lvpecl f igure 4d. h i p er c lock s pclk/npclk i nput d riven by a 3.3v lvpecl d river with ac c ouple 3.3v 3.3v cml built-in pullup r1 100 pclk npclk hiperclocks pclk/npclk zo = 50 ohm zo = 50 ohm
873032am www.icst.com/products/hiperclocks.html rev. a august 11, 2004 9 integrated circuit systems, inc. ICS873032 h igh s peed , 2 d ifferential - to - 3.3v, 5v lvpecl/ecl c lock g enerator preliminary p ower c onsiderations this section provides information on power dissipation and junction temperature for the ICS873032. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS873032 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 5.5v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 5.5v * 22ma = 121mw ? power (outputs) max = 30.94mw/loaded output pair if all outputs are loaded, the total power is 1 * 30.94mw = 30.94mw total power _max (5.5v, with all outputs switching) = 121mw + 30.94mw = 151.9mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3c/w per table 6a below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.152w * 103.3c/w = 100.7c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 153.3c/w 128.5c/w 115.5c/w multi-layer pcb, jedec standard test boards 112.7c/w 103.3c/w 97.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 6a. t hermal r esistance ja for 8- pin soic, f orced c onvection t able 6b. t hermal r esistance ja for 8- pin tssop, f orced c onvection ja by velocity (meters per second) 012 multi-layer pcb, jedec standard test boards 101.7c/w 90.5c/w 89.8c/w
873032am www.icst.com/products/hiperclocks.html rev. a august 11, 2004 10 integrated circuit systems, inc. ICS873032 h igh s peed , 2 d ifferential - to - 3.3v, 5v lvpecl/ecl c lock g enerator preliminary 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 5. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc - 2v. for logic high, v out = v oh_max = v cc_max ?0.935v (v cc_max - v oh_max ) = 0.935v for logic low, v out = v ol_max = v cc_max ? 1.67v (v cc_max - v ol_max ) = 1.67v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc_max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 0.935v)/50 ? ] * 0.935v = 19.92mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc_max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.67v)/50 ? ] * 1.67v = 11.02mw total power dissipation per output pair = pd_h + pd_l = 30.94mw f igure 5. lvpecl d river c ircuit and t ermination vout q1 vcc - 2v rl 50 vcc
873032am www.icst.com/products/hiperclocks.html rev. a august 11, 2004 11 integrated circuit systems, inc. ICS873032 h igh s peed , 2 d ifferential - to - 3.3v, 5v lvpecl/ecl c lock g enerator preliminary r eliability i nformation t ransistor c ount the transistor count for ICS873032 is: 165 t able 7a. ja vs . a ir f low t able for 8 l ead soic ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 153.3c/w 128.5c/w 115.5c/w multi-layer pcb, jedec standard test boards 112.7c/w 103.3c/w 97.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 7b. ja vs . a ir f low t able for 8 l ead tssop ja by velocity (meters per second) 012 multi-layer pcb, jedec standard test boards 101.7c/w 90.5c/w 89.8c/w
873032am www.icst.com/products/hiperclocks.html rev. a august 11, 2004 12 integrated circuit systems, inc. ICS873032 h igh s peed , 2 d ifferential - to - 3.3v, 5v lvpecl/ecl c lock g enerator preliminary p ackage o utline - m s uffix for 8 l ead soic t able 8a. p ackage d imensions reference document: jedec publication 95, ms-012 l o b m y s s r e t e m i l l i m n u m i n i mm u m i x a m n8 a5 3 . 15 7 . 1 1 a0 1 . 05 2 . 0 b3 3 . 01 5 . 0 c9 1 . 05 2 . 0 d0 8 . 40 0 . 5 e0 8 . 30 0 . 4 ec i s a b 7 2 . 1 h0 8 . 50 2 . 6 h5 2 . 00 5 . 0 l0 4 . 07 2 . 1 0 8
873032am www.icst.com/products/hiperclocks.html rev. a august 11, 2004 13 integrated circuit systems, inc. ICS873032 h igh s peed , 2 d ifferential - to - 3.3v, 5v lvpecl/ecl c lock g enerator preliminary p ackage o utline - g s uffix for 8 l ead tssop t able 8b. p ackage d imensions reference document: jedec publication 95, mo-187 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n8 a- -0 1 . 1 1 a0 5 1 . 0 2 a9 7 . 07 9 . 0 b2 2 . 08 3 . 0 c8 0 . 03 2 . 0 dc i s a b 0 0 . 3 ec i s a b 0 9 . 4 1 ec i s a b 0 0 . 3 ec i s a b 5 6 . 0 1 ec i s a b 5 9 . 1 l0 4 . 00 8 . 0 0 8 a a a- -0 1 . 0
873032am www.icst.com/products/hiperclocks.html rev. a august 11, 2004 14 integrated circuit systems, inc. ICS873032 h igh s peed , 2 d ifferential - to - 3.3v, 5v lvpecl/ecl c lock g enerator preliminary t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extr aordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pt n u o ce r u t a r e p m e t m a 2 3 0 3 7 8 s c i2 3 0 3 7 8c i o s d a e l 8e b u t r e p 6 9c 5 8 o t c 0 4 - t m a 2 3 0 3 7 8 s c i2 3 0 3 7 8l e e r d n a e p a t n o c i o s d a e l 80 0 5 2c 5 8 o t c 0 4 - g a 2 3 0 3 7 8 s c i2 3 0p o s s t d a e l 8e b u t r e p 6 9c 5 8 o t c 0 4 - t g a 2 3 0 3 7 8 s c i2 3 0l e e r d n a e p a t n o p o s s t d a e l 80 0 5 2c 5 8 o t c 0 4 - the aforementioned trademark, hiperclocks? is a trademark of integrated circuit systems, inc. or its subsidiaries in the unite d states and/or other countries.

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